library ieee;
use ieee.std_logic_1164.all;
entity dmux_1t8 is
port (
input, sel2, sel1, sel0 : in std_logic;
output0, output1, output2, output3, output4, output5, output6, output7 : out std_logic);
end dmux_1t8;
architecture dmux_1t8_ar of dmux_1t8 is
begin -- dmux_1t8_ar
output0 <=input and(not sel2)and(not sel1)and(not sel0);
output1 <=input and(not sel2)and(not sel1)and sel0;
output2 <=input and(not sel2)and sel1 and(not sel0);
output3 <=input and(not sel2)and sel1 and sel0;
output4 <=input and sel2 and(not sel1)and(not sel0);
output5 <=input and sel2 and(not sel1)and sel0;
output6 <=input and sel2 and sel1 and(not sel0);
output7 <=input and sel2 and sel1 and sel0;
end dmux_1t8_ar;