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Friday, November 27, 2015

Dear Students

Dear Students,

If u want any help in VLSI then put ur questions in comment line.

Thank u!!!!

Thursday, July 26, 2012

VHDL code for Gray to Binary Code Converter




Binary code equivalent of the given gray number is computed as follows:
b3 = g3
b2 = b3 ⊕ g2
b1 = b2 ⊕ g1
b0 = b1 ⊕ g0


library ieee;
use ieee.std_logic_1164.all;


entity gtb_vhd is
  port (
    g :in  std_logic_vector(3 downto 0);
    b :inout std_logic_vector(3 downto 0));
  
end gtb_vhd;


architecture gtb_vhd_ar of gtb_vhd is


begin  -- gtb_vhd_ar


  b(3)<=g(3);
  b(2)<=b(3) xor g(2);
  b(1)<=b(2) xor g(1);
  b(0)<=b(1) xor g(0);


end gtb_vhd_ar;

VHDL code for Comparator


library ieee;
use ieee.std_logic_1164.all;


entity comparator is
  
  port (
    a, b    : in  std_logic;
    d        :out std_logic;
    c, e    :inout std_logic);
  
end comparator;


architecture comparator_ar of comparator is


begin  -- comparator_ar


  c <=(not a) and b;
  e <=a and (not b);
  d <=c nor e;


end comparator_ar;


Sunday, July 22, 2012

VHDL code for 1x8 Demultiplexer



library ieee;
use ieee.std_logic_1164.all;

entity dmux_1t8 is

 port (
   input, sel2, sel1, sel0  : in  std_logic;
   output0, output1, output2, output3, output4, output5, output6, output7 : out std_logic);

end dmux_1t8;

architecture dmux_1t8_ar of dmux_1t8 is

begin  -- dmux_1t8_ar

  output0 <=input and(not sel2)and(not sel1)and(not sel0);
  output1 <=input and(not sel2)and(not sel1)and sel0;
  output2 <=input and(not sel2)and sel1 and(not sel0);
  output3 <=input and(not sel2)and sel1 and sel0;
  output4 <=input and sel2 and(not sel1)and(not sel0);
  output5 <=input and sel2 and(not sel1)and sel0;
  output6 <=input and sel2 and sel1 and(not sel0);
  output7 <=input and sel2 and sel1 and sel0;

end dmux_1t8_ar;

VHDL code for 1x2 Demultiplexer


library ieee;
use ieee.std_logic_1164.all;

entity dmux_1t2 is
 
  port (
    input   : in  std_logic;
    sel0    : in  std_logic;
    output0 : out std_logic;
    output1 : out std_logic);
 
end dmux_1t2;

architecture dmux_1t2_ar of dmux_1t2 is

begin  -- dmux_1t2_ar


output0 <=input and(not sel0);
output1 <=input and sel0;

end dmux_1t2_ar;