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Thursday, July 26, 2012

VHDL code for Gray to Binary Code Converter




Binary code equivalent of the given gray number is computed as follows:
b3 = g3
b2 = b3 ⊕ g2
b1 = b2 ⊕ g1
b0 = b1 ⊕ g0


library ieee;
use ieee.std_logic_1164.all;


entity gtb_vhd is
  port (
    g :in  std_logic_vector(3 downto 0);
    b :inout std_logic_vector(3 downto 0));
  
end gtb_vhd;


architecture gtb_vhd_ar of gtb_vhd is


begin  -- gtb_vhd_ar


  b(3)<=g(3);
  b(2)<=b(3) xor g(2);
  b(1)<=b(2) xor g(1);
  b(0)<=b(1) xor g(0);


end gtb_vhd_ar;

4 comments:

  1. Good post. I will be going through many of these issues as well..


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  2. Logic is correct but the implementation in xilinx is not correct. Because you make the program in dataflow modelling and in dataflow, all the steps run at same time. So the input to the second step is not available at that time and you get an error while compiling.

    Thanks

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  3. Keep doing what you're doing! You just saved my grade :,)

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