EXNOR GATE

library ieee;
use ieee.std_logic_1164.all;

entity xnor_gate is

port (

a: in std_logic;
b: in std_logic;
y: out std_logic);

end xnor_gate;

architecture xnor_gate_ar of xnor_gate is

begin

y <= a xnor b;

end xnor_gate_ar;

EXOR GATE

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is

port (

a: in std_logic;
b: in std_logic;
y: out std_logic);

end xor_gate;

architecture xor_gate_ar of xor_gate is

begin

y <= a xor b;

end xor_gate_ar;

NOR GATE

library ieee;
use ieee.std_logic_1164.all;

entity nor_gate is

port (

a: in std_logic;
b: in std_logic;
output: out std_logic);

end nor_gate;

architecture nor_gate_ar of nor_gate is

begin

y <= a nor b;

end nor_gate_ar;

NAND GATE

library ieee;
use ieee.std_logic_1164.all;

entity nand_gate is

port (

a: in std_logic;
b: in std_logic;
output: out std_logic);

end nand_gate;

architecture nand_gate_ar of nand_gate is

begin

y <= a nand b;

end nand_gate_ar;

NOT GATE

library ieee;
use ieee.std_logic_1164.all;

entity not_gate is

port (
     
        x: in std_logic;
        output: out std_logic);

end not_gate;

architecture not_gate_ar of not_gate is

begin

y <= not x;

end not_gate_ar;

OR GATE

library ieee;
use ieee.std_logic_1164.all;

entity or_gate is

port (
       
        a: in std_logic;
        b:in std_logic;
        y:out std_logic);

end or_gate;

architecture or_gate_ar of or_gate is

begin

y <= a or b;

end or_gate_ar;

VHDL & VERILOG

VHDL (Very High speed integrated circuit Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
                                                                        
                                                                        &


Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level of abstraction. It is also used in the verification of analog and mixed-signal circuits.

Difference Between Verilog and VHDL

Verilog vs. VHDL

Verilog and VHDL are Hardware Description languages that are used to write programs for electronic chips. These languages are used in electronic devices that do not share a computer’s basic architecture. VHDL is the older of the two, and is based on Ada and Pascal, thus inheriting characteristics from both languages. Verilog is relatively recent, and follows the coding methods of the C programming language.

VHDL is a strongly typed language, and scripts that are not strongly typed, are unable to compile. A strongly typed language like VHDL does not allow the intermixing, or operation of variables, with different classes. Verilog uses weak typing, which is the opposite of a strongly typed language. Another difference is the case sensitivity. Verilog is case sensitive, and would not recognize a variable if the case used is not consistent with what it was previously. On the other hand, VHDL is not case sensitive, and users can freely change the case, as long as the characters in the name, and the order, stay the same.

In general, Verilog is easier to learn than VHDL. This is due, in part, to the popularity of the C programming language, making most programmers familiar with the conventions that are used in Verilog. VHDL is a little bit more difficult to learn and program.

VHDL has the advantage of having a lot more constructs that aid in high-level modeling, and it reflects the actual operation of the device being programmed. Complex data types and packages are very desirable when programming big and complex systems, that might have a lot of functional parts. Verilog has no concept of packages, and all programming must be done with the simple data types that are provided by the programmer.

Lastly, Verilog lacks the library management of software programming languages. This means that Verilog will not allow programmers to put needed modules in separate files that are called during compilation. Large projects on Verilog might end up in a large, and difficult to trace, file.

Summary:

1. Verilog is based on C, while VHDL is based on Pascal and Ada.

2. Unlike Verilog, VHDL is strongly typed.

3. Ulike VHDL, Verilog is case sensitive.

4. Verilog is easier to learn compared to VHDL.

5. Verilog has very simple data types, while VHDL allows users to create more complex data types.

6. Verilog lacks the library management, like that of VHDL.

AND GATE

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is

port (

a : in std_logic;
b: in std_logic;
y: out std_logic);

end and_gate;

architecture and_gate_ar of and_gate is

begin

y <= a and b;

end and_gate_ar;