EXNOR GATE

library ieee;
use ieee.std_logic_1164.all;

entity xnor_gate is

port (

a: in std_logic;
b: in std_logic;
y: out std_logic);

end xnor_gate;

architecture xnor_gate_ar of xnor_gate is

begin

y <= a xnor b;

end xnor_gate_ar;