VHDL code for Half Adder

library ieee;
use ieee.std_logic_1164.all;

entity half_add is

port (

a : in std_logic;

b : in std_logic;
sum : out std_logic;

carry : out std_logic);

end half_add;

architecture half_add_ar of half_add is

begin

sum <= a xor b;
carry <= a and b;

end half_add_ar;