VHDL code for 4x1 Multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity mux_4t1 is

  port (
    in0    : in  std_logic;
    in1    : in  std_logic;
    in2    : in  std_logic;
    in3    : in  std_logic;
    sel1   : in  std_logic;
    sel0   : in  std_logic;
    output : out std_logic);
 
end mux_4t1;

architecture mux_4t1_ar of mux_4t1 is
signal temp1,temp2,temp3,temp4 : std_logic;

begin  -- mux_4t1_ar

  temp1 <= in0 and(not sel1)and(not sel0);
  temp2 <= in1 and(not sel1)and(not sel0);
  temp3 <= in3 and sel1 and sel0;
  temp4 <= in2 and sel1 and (not sel0);
  output <= temp1 or temp2 or temp3 or temp4;

end mux_4t1_ar;