VHDL code for Full Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_add is

  port (
    a    : in  std_logic;
    b    : in  std_logic;
    cin  : in  std_logic;
    sum  : out std_logic;
    cout : out std_logic);
   
end full_add;

architecture full_add_ar of full_add is
signal temp1,temp2,temp3 : std_logic;

begin  -- full_add_ar

  temp1 <=a xor b;
  sum <= temp1 xor cin;
  temp2 <=temp1 and cin;
  temp3 <= a and b;
  cout <=temp2 or temp3;
 

end full_add_ar;