VHDL code for half subtractor

library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port (

a : in std_logic;

b : in std_logic;

diff : out std_logic;

bor : out std_logic);

end half_sub;

architecture half_sub_ar of half_sub is

begin

diff <= a xor b;

bor <= (not a) and b;

end half_sub_ar;