use ieee.std_logic_1164.all;
entity parity_checker is
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
p : out std_logic);
end parity_checker;
architecture parity_checker_ar of parity_checker is
signal r,s : std_logic;
begin -- parity_checker_ar
r <= a0 xor a1;
s <= a2 xor r;
p <= s xor a3;
end parity_checker_ar;
hello students if u need any help in VLSI then comment me here. Thank u
ReplyDeleteCan you give a verilog code for 8 bit odd parity generator and checker
ReplyDeleteHello, i know i am come late but i think this code will not properly functional as the assignments here are non-blocking which means they are simultaneously updated so even if you initialize the values of the signal r & s with some values ( zeros or ones) you still have the wrong values to be Xored. thanks
ReplyDelete