VHDL code for Full Subtractor

library ieee;
use ieee.std_logic_1164.all;

entity full_subtractor is

 port (
   a       : in    std_logic;
   b       : in    std_logic;
   c       : in    std_logic;
   d       : out   std_logic;
   borrow: out   std_logic;
   o       : inout std_logic;      
   p       : inout std_logic;
   q       : inout std_logic);

end full_subtractor;

architecture full_subtractor_ar of full_subtractor is

begin  -- full_subtractor_ar

  d <= a xor b xor c;
  o <=(not a)and b;
  p <=(not a)and c;
  q <= b and c;
  borrow <=o or p or q;

end full_subtractor_ar;