Comparison of VHDL and Verilog

VHDL	Verilog
1. Data types are defined by user.	1. Data types are defined by Verilog instead of the user.
2. Procedures and functions may be put in a package for sharing in any design unit that need them.	2. No packages in Verilog.  Procedures and functions used within a model must be defined in the module.
3. Has a library for managing a number of designs.	3. Has no concept of library.
4. Similar to Ada or Pascal.	4. Similar to C or C++.
5. A wordy language.	5. A language that provide brevity.