3x8 line decoder

library ieee;
use ieee.std_logic_1164.all;

entity deco_ckt is
 
  port (
    a  : in  std_logic;
    b  : in  std_logic;
    c  : in  std_logic;
    d0 : out std_logic;
    d1 : out std_logic;
    d2 : out std_logic;
    d3 : out std_logic;
    d4 : out std_logic;
    d5 : out std_logic;
    d6 : out std_logic;
    d7 : out std_logic);
 
end deco_ckt;

architecture deco_ckt_ar of deco_ckt is

begin  -- deco_ckt_ar

  d0 <= (not a)and (not b)and (not c);
  d1 <= (not a)and (not b)and c;
  d2 <= (not a)and b and (not c);
  d3 <= (not a)and b and c;
  d4 <= a and (not b)and(not c);
  d5 <= a and (not b)and c;
  d6 <= a and b and (not c);
  d7 <= a and b and c;

end deco_ckt_ar;