VHDL code for 2x4 line Decoder

library ieee;
use ieee.std_logic_1164.all;

entity deco_2t4 is

  port (
    a  : in  std_logic;
    b  : in  std_logic;
    d0 : out std_logic;
    d1 : out std_logic;
    d2 : out std_logic;
    d3 : out std_logic);

end deco_2t4;

architecture deco_2t4_ar of deco_2t4 is

begin  -- deco_2t4_ar

  d0 <= (not a)and (not b);
  d1 <= (not a)and b;
  d2 <= a and (not b);
  d3 <= a and b;

end deco_2t4_ar;