VHDL code for BCD-to-Decimal Decoder

library ieee;
use ieee.std_logic_1164.all;

entity bcdtod1_ckt is
 
port (
  a0  : in  std_logic;
  a1  : in  std_logic;
  a2  : in  std_logic;
  a3  : in  std_logic;
  d0 : out std_logic;
  d1 : out std_logic;
  d2 : out std_logic;
  d3 : out std_logic;
  d4 : out std_logic;
  d5 : out std_logic;
  d6 : out std_logic;
  d7 : out std_logic;
  d8 : out std_logic;
  d9 : out std_logic);

end bcdtod1_ckt;

architecture bcdtod1_ckt_ar of bcdtod1_ckt is

begin  -- bcdtod1_ckt_ar

  d0 <= (not a0)and(not a1)and(not a2)and(not a3);
  d1 <= a0 and(not a1)and(not a2)and(not a3);
  d2 <= (not a0)and a1 and(not a2)and(not a3);
  d3 <= a0 and a1 and (not a2)and(not a3);
  d4 <= (not a0)and(not a1)and a2 and (not a3);
  d5 <= a0 and (not a1)and a2 and(not a3);
  d6 <= (not a0)and a1 and a2 and (not a3);
  d7 <= a0 and a1 and a2 and (not a3);
  d8 <= (not a0)and(not a1)and(not a2)and a3;
  d9 <= a0 and (not a1)and(not a2)and a3;
 

end bcdtod1_ckt_ar;