VHDL code for D-flip flop

library ieee;
use ieee.std_logic_1164.all;

entity d_ff is
port (d : in std_logic;
clock : in std_logic;
q : out std_logic);
end d_ff;

architecture d_ff_ar of d_ff is

begin
process(clock)
begin

if (clock'event and clock='1') then
q <=d;

end if;
end process;
end d_ff_ar;