VHDL code for 2x1 Multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity mux_2t1 is

 port (
   in0    : in  std_logic;
   in1    : in  std_logic;
   sel    : in  std_logic;
   output : out std_logic);

end mux_2t1;

architecture mux_2t1_ar of mux_2t1 is
signal temp1,temp2 : std_logic;

begin  -- mux_2t1_ar

  temp1 <=in0 and (not sel);
  temp2 <=in1 and sel;
  output <=temp1 or temp2;

end mux_2t1_ar;