VHDL code for 8x1 multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity mux_8t1 is

 port (
   in0    : in  std_logic;
   in1    : in  std_logic;
   in2    : in  std_logic;
   in3    : in  std_logic;
   in4    : in  std_logic;
   in5    : in  std_logic;
   in6    : in  std_logic;
   in7    : in  std_logic;
   sel2   : in std_logic;
   sel1   : in std_logic;
   sel0   : in std_logic;
   output : out std_logic);

end mux_8t1;

architecture mux_8t1_ar of mux_8t1 is
signal o,p,q,r,s,t,u,v : std_logic;
begin  -- mux_8t1_ar

  o<= in0 and(not sel2)and(not sel1)and(not sel0);
  p<= in1 and(not sel2)and(not sel1)and sel0;
  q<= in2 and(not sel2)and sel1 and(not sel0);
  r<= in3 and(not sel2)and sel1 and sel0;
  s<= in4 and sel2 and(not sel1)and(not sel0);
  t<= in5 and sel2 and(not sel1)and sel0;
  u<= in6 and sel2 and sel1 and(not sel0);
  v<= in7 and sel2 and sel1 and sel0;
  output <= o or p or q or r or s or t or u or v;

  end mux_8t1_ar;