VHDL code for 1x4 Demultiplexer

library ieee;
use ieee.std_logic_1164.all;

entity dmux_1t4 is
 
port (
  input   : in  std_logic;
  sel1    : in  std_logic;
  sel0    : in  std_logic;
  output0 : out std_logic;
  output1 : out std_logic;
  output2 : out std_logic;
  output3 : out std_logic);

end dmux_1t4;

architecture dmux_1t4_ar of dmux_1t4 is

begin  -- dmux_1t4_ar

  output0 <=input and(not sel1)and(not sel0);
  output1 <=input and(not sel1)and sel0;
  output2 <=input and sel1 and(sel0);
  output3 <=input and sel1 and sel0;

end dmux_1t4_ar;