VHDL code for 1x2 Demultiplexer

library ieee;
use ieee.std_logic_1164.all;

entity dmux_1t2 is
 
  port (
    input   : in  std_logic;
    sel0    : in  std_logic;
    output0 : out std_logic;
    output1 : out std_logic);
 
end dmux_1t2;

architecture dmux_1t2_ar of dmux_1t2 is

begin  -- dmux_1t2_ar


output0 <=input and(not sel0);
output1 <=input and sel0;

end dmux_1t2_ar;