VHDL code for Comparator

library ieee;
use ieee.std_logic_1164.all;


entity comparator is
  
  port (
    a, b    : in  std_logic;
    d        :out std_logic;
    c, e    :inout std_logic);
  
end comparator;


architecture comparator_ar of comparator is


begin  -- comparator_ar


  c <=(not a) and b;
  e <=a and (not b);
  d <=c nor e;


end comparator_ar;